The present invention relates to a semiconductor device which is suitable, for example, for an MRAM (Magnetic Random Access Memory).
In recent years, MRAMs have been attracting attention as semiconductor devices which can store nonvolatile data at low power consumption. An MRAM includes a plurality of memory cells MC disposed in a plurality of rows and a plurality of columns, a plurality of digit lines DL located in a way to correspond to the rows respectively and a plurality of bit lines BL located in a way to correspond to the columns. In write operation, current Im is supplied to selected digit lines DL to activate the memory cells corresponding to the digit lines DL and write current Iw whose direction depends on the logic level of a data signal is supplied to selected bit lines BL. Consequently the data signal is written in the memory cells MC located at the intersections between the selected digit lines DL and bit lines BL.
In order to reduce noise caused by voltage fluctuations in power wiring and grounding wiring, some MRAMs include a capacitor coupled between power wiring and grounding wiring (for example, see Japanese Unexamined Publication No. 2005-303156 and Japanese Unexamined Patent Publication No. 2011-3768).